Application specific integrated circuits are chips that are manufactured with a fixed design. In general, FPGAs are slower and consume more power and area than an ASIC implementation. However, some newer high-end FPGAs can match the performance of an ASIC.
FPGAs (Field Programmable Gate Arrays) are chips created originally in 1985 to perform only digital functions but today they have already both analog and mixed signal blocks. Customers like to use FPGA because they are easy to use, and cost effective reprogrammable devices. FPGA are known for their flexibility and their ability to be reprogrammed in the field. There is no need to have a full blown design flow and tooling, therefore the NRE investment is very low and as consequence time to market is fast.
The problem is that FPGAs are not fully customable, for example, one cannot add a specific analog block or integrate RF capability into an FPGA, those functionalities need to be implemented by external ICs, thus making the product larger in size and more costly.
ASICs (Application Specific Integrated Circuits) are specific chips (as the name suggest) used to implement both analog and digital functionalities in high volume or high performance. ASICs are full custom therefore they require higher development costs in order to design and implement (NRE). Moreover, unlike the FPGAs chips, they are not reprogrammable and therefore a change requires again NRE payment.
On the other side, however, ASICS are much denser, and one can integrate several different functionalities into one chip and therefore offer small size, low power and low cost solution.
FPGAs do have two significant advantages over ASICs.
First, FPGA systems are much cheaper than a custom chip, especially in low quantities.
In addition to designing the behavioral model, an ASIC requires the physical design of the chip die itself as well as silicon wafer manufacturing, which is not cheap.
Second, FPGAs can be reprogrammed, while an ASIC is permanent.
In fact, even when the end goal is an ASIC, most engineers will use an FPGA for testing purposes in order to work out any problems; design of the behavioral model is virtually identical.