A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence the term “field-programmable”. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an Application-Specific Integrated Circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools.
FPGAs contain an array of programmable logic blocks, and a hierarchy of “reconfigurable interconnects” that allow the blocks to be “wired together”, like many logic gates that can be inter-wired in different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
A logic block, sometimes called configurable logic block is a component of an FPGA. Each logic block can be configured to hold a number of logic gates, which are interconnected. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigurable computing as performed in computer software.
From the name, one might infer that it is a programmable structure of logic gates. This is close, but not accurate because the internal logic array isn’t actually implemented with gates. Instead, we refer to the blocks in the array as logic elements. These normally consist of a lookup table (LUT) that implements an arbitrary logic function as well as some supporting circuitry like multiplexers, adders, and flip-flops. A LUT is a small block of memory that models any Boolean function as a truth table. You’ll often hear this array of logic elements referred to as the “FPGA fabric.”
Often, the LUT will have a built-in full adder—notice the carry in (CI) and carry out (CO) pins, more on this below. This simple diagram only has a 4-input LUT, but in practice, most modern FPGAs use 6-input tables to improve performance.
The output of the logic cell is multiplexed. One option is a direct output from the LUT, used for pure combinational logic such as AND and OR gates. Alternatively, the LUT output can be fed into a D-type flip-flop and stored synchronously with the clock.
The logic cell is a neat little piece of circuitry, but the magic behind the FPGA is just beginning. In order to implement complex logic functions, each individual logic cell can be connected to a host of others.
The big circles in the middle of the diagram represent programmable switches that can route the output from a logic cell pretty much anywhere. Again, this is a simplified diagram; in a practical FPGA there are many more wires and interconnects than depicted here.
The LUTs have built-in adders, Each adder is typically only one bit wide, so the carry in/carry out pins are necessary in order to create larger adders and counters quickly and efficiently. The inclusion of fast, dedicated carry chains is one of the most significant advantages FPGAs have over other programmable logic.
I like to think of an FPGA as a box of colorful, non-trademarked building blocks for creating digital circuits. I can connect the blocks together any way that I want to fit my application. If you can describe how a digital circuit behaves, you can create it inside an FPGA with enough logic elements. Need 25 PWM outputs? No problem. Need a special communication protocol? Write some hardware to handle it.
Since digital designs generally rely heavily on clocks, it’s important that an FPGA has advanced clocking resources. Clock signals have to reach every flip-flop on every logic cell on the entire chip distortion free and with as little clock skew as possible. An FPGA will have numerous global clock lines that adhere to these strict timing requirements.
What’s the point of having such a terrific clock distribution system if there’s nothing to drive it with? An advanced digital design will usually require multiple clock signals of different speeds, and there needs to be some way of providing all the individual frequencies from one common source. This is where clock management comes into play. Digital clock managers (DCM) can multiply and divide a reference clock input to create a range of output frequencies, as well as controlling clock phase. In addition, phase-locked loops (PLL) can be used to synthesize almost any frequency imaginable.
Finally, there must be some way to bring data in and out of the chip. In addition to standard I/O, a typical FPGA may provide some other I/O capabilities:
- Flip-flop output for synchronous I/O
- Differential signaling
- Double data rate (DDR)
- Serializers and deserializers (SERDES)
- Pull-up, pull-down, and tri-state I/O
- Adjustable slew rate, drive strength
The behavior of an FPGA can be specified by using a hardware description language (HDL), such as Verilog or VHDL, or by drawing a schematic. Schematic entry is relatively uncommon for large designs, as it is often easier to use an HDL. The behavioral model is usually then tested rigorously on a computer to identify and fix any bugs or problems that may arise.
Once the design has been finalized, it is time to place it on the chip. First, a software program synthesizes the design and creates a netlist, or a list of all the logic cells and connections that are needed. Next, a place-and-route algorithm figures out the most optimal way to map the netlist to the chip. There are many parameters that affect how a design will be routed, including performance, power consumption, and area. Finally, the design is ready to be uploaded to the FPGA. This is where all the LUTs are configured, the multiplexers and switches set, and all the I/O and clock resources are programmed.
One drawback with FPGAs is that most are volatile, meaning that once power is removed from the chip, the design is lost and must be reprogrammed. External flash memories must be used in order to retain the design, and most development boards include this functionality.
A massive array of logic cells, some good clocking resources, and tons of I/O make for a great digital system in itself, but by including additional features directly on the chip, an FPGA can gain even more functionality. Dedicated circuitry is almost always faster and more power efficient than a similar component assembled from logic cells, not to mention significantly smaller in terms of chip area.
Nearly all FPGAs have some amount of built-in memory. The main memory type is called block RAM. Scattered throughout the chip are dedicated SRAM blocks. Block RAM is the ultimate on-chip memory resource; it is speedy, power efficient, and takes up the least area. However, there are a limited number of blocks on a chip, and each generally has a finite amount of space. Distributed RAM is another type of memory which uses a bunch of logic cells as very, very small memory units. Distributed RAM is very space-inefficient, but it works well for small memory sizes (up to a few hundred bytes), after which block RAM becomes a better choice. An FPGA might have between 100Kb and 100Mb of dedicated block RAM, and about a quarter as much available distributed RAM.
A common feature in newer FPGAs are DSP multiplier slices. For arithmetic-heavy digital signal processing applications, you can’t beat a dedicated DSP slice for performance and power. Each slice typically consists of a multiplier and several adders. A basic DSP slice might be able to perform the expression listed below.
This is called a multiplier with pre-adder, and is the foundation of all DSP slices. Slices can be cascaded to create larger multipliers and more complex arithmetic functions. Entry-level FPGAs might have a few dozen slices, while higher end models might have several thousand.
Other common peripherals include the following:
- External memory controller (DRAM, DDR, DDR2, etc.)
- Ethernet MAC (fast and gigabit)
- Dedicated FIFO
- High-speed transceivers
- PCI Express controllers
- ADC and DAC
Some FPGAs has built-in hard blocks such as Memory controllers, high-speed communication interfaces, PCIe Endpoints, etc. But the point is, there are a lot of gates inside the FPGA which can be arbitrarily connected together to make a circuit of your choice. More or less like connecting individual logic gate ICs (again oversimplified but a good mental picture nonetheless). FPGAs are manufactured by companies like FII, Xilinx, Altera, Microsemi, etc… FPGAs are fundamentally similar to CPLDs but CPLDs are very small in size and capability compared to FPGAs.
Above is a FPGA study board for beginner. developed by FII.
The advantage of FPGA beginner study board:
- Beginner FPGA study board, cheaper but fully functional. cellphone sized. ( < 100 USD )
- power supply and download at the same time, no extra power supply and no extra data transfer line needed
- Small volume and light and can be put into your pocket. size: 10cm X 7 cm.
- Unique function: can be a study board as well a multifunctional JTAG downloader.
- We use newest version Intel FPGA within two years and you can always keep in the front of FPGA industry.
Altera FPGA Study Board Hardware Resources：
- 6 seven_seg_r
- VGA Video Interface × 1
- 1G Ethernet Interface × 1
- I2C EEPROM × 1
- DIP Switch × 8
- Controllable LED light × 8
- Photoresistance × 1
- Thermistor × 1
- Adjustable Varistor × 1
- Buttons × 4
- GPIO Interface × 2
- Micro usb Interface（Power Supply and downlaod ) × 1
- SPI Communication Interface × 1
- AD/DA Conversion chip × 1
- JTAG Download Interface × 1
- FLASH 32Mbit × 1
The Benefits of FPGA
- FPGA functionality can change upon every power-up of the device. So, when a design engineer wants to make a change, they can simply download a new configuration file into the device and try out the change.
- Often, changes can be made to the FPGA without making costly PC board changes.
- ASSPs and ASICs have fixed hardware functionality that can’t be changed without great cost and time.
- FPGAs are sold “off the shelf” vs. ASICs (which require manufacturing cycles taking many months).
- Because of FPGA flexibility, OEMs can ship systems as soon as the design is working and tested.
- FPGAs provide off-load and acceleration functions to CPUs, effectively speeding up the entire system performance.
Today’s FPGAs include on-die processors, transceiver I/O’s at 28 Gbps (or faster), RAM blocks, DSP engines, and more. More functions within the FPGA mean fewer devices on the circuit board, increasing reliability by reducing the number of device failures.