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FPGA for Student Code

FPGA Beginner Board
FPGA Beginner Board

The experiment is based on FII-FPGA Beginner Board

You can buy it here:

https://fpgamarketing.com/FPGA-Study-Board-Verilog-for-beginner-Cyclone-10-FII-PRA006-FII-PRA006.htm

FII-PRA006 Experiment 1 LED_shifting

module LED_shifting (clk, rst, led);
input clk, rst; output [7:0] led;
endmodule

For experiment procedure, please check fpga beginner tutor

Loopback test design (test1)

The loopback test is straightforward. Simply output the input data. Code is shown as below:

module test1 (rxc, rxdv, rxd, txc, txen, txd);
input rxc;
input rxdv;
input [3:0] rxd;

output txc;
output txen;
output [3:0] txd; 

assign txd = rxd;
assign txen = rxdv;
assign txc = rxc;
endmodule

We include the PLL1 generated in Experiment 1 Verilog HDL code is as follows:

module SW_LED(

input inclk,
input [7:0] sw,
output reg [7:0] led
);

wire sys_clk;
wire pll_locked;
reg sys_rst;

always@(posedge sys_clk)
sys_rst<=!pll_locked;

always @(posedge inclk)
if(sys_rst)
led<=8’hff;
else
led<=~sw;

PLL1 PLL1_INST

(
.areset (1’b0),
.inclk0 (inclk),
.c0 (sys_clk),
.locked (pll_locked)
);

endmodule

segment decoder code

always	@	 (*)

case(count_sel)

0:seven_seg_r<=7'b100_0000;

1:seven_seg_r<=7'b111_1001;

2:seven_seg_r<=7'b010_0100;

3:seven_seg_r<=7'b011_0000;

4:seven_seg_r<=7'b001_1001;

5:seven_seg_r<=7'b001_0010;

6:seven_seg_r<=7'b000_0011;

7:seven_seg_r<=7'b111_1000;

8:seven_seg_r<=7'b000_0000;

9:seven_seg_r<=7'b001_0000;

default:seven_seg_r<=7'b100_0000;

endcase

always @ (posedge sys_clk)

seven_seg<={1'b1,seven_seg_r};

For more FPGA board experimental Tutorials, please go to following websites:
https://fraserinnovations.com/fpga_products/cyclone-10-fpga-board-experimental-manuals/

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